The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a plurality of power transistors and formed to enable miniaturization of the power transistors and improve operational stability of the power transistors.
As electronics devices have been miniaturized and manufactured at lower cost, power transistors mounted on such electronics devices are also required to be miniaturized. In particular, electronics devices having withstand voltages of 100 V or lower, such as portable devices and household appliances, are required to be further miniaturized. Thus, such electronics devices inevitably require techniques for integrating a control circuit and a plurality of power transistors on a single semiconductor substrate. A lateral double diffused metal oxide semiconductor field effect transistor (LDMOSFET), which is one conventional transistor structure that enables easy integration of a plurality of semiconductor elements, has been widely commercialized.
A typical LDMOSFET has a drift region formed at a drain side to increase its withstand voltage. The drift region is generally required to have a length of approximately 0.067 μm/V. To manufacture an LDMOSFET having a withstand voltage of, for example, 20 V, a drift region having a length of approximately 1.34 micrometers needs to be formed using a submicron fabrication technique. The withstand voltage of the LDMOSFET is improved by forming the drift region at the drain side. However, the drift region limits the miniaturization of the LDMOSFET.
Japanese Patent No. 3348911 and Japanese Laid-Open Patent Publication No. 2002-184980 describe improved DMOSFETs. In such an improved DMOSFET, a source wire and a drain wire are extended from the surface of a substrate, and a trench is formed in the substrate in the depthwise direction of the substrate. A gate electrode is arranged in the trench by an insulation film. Regions close to the side walls of the trench in the semiconductor substrate are formed as a channel layer and a drift layer. This structure miniaturizes the DMOS transistor.
The DMOSFET structures described in Japanese Patent No. 3348911 and Japanese Laid-Open Patent Publication No. 2002-184980 enable reduction in the area occupied by a single semiconductor element on a semiconductor substrate as compared with the conventional LDMOSFET. A plurality of power semiconductor elements are normally connected in parallel to drive a large load. As the area of each semiconductor element decreases, the region in which metal wires are arranged for connection between the semiconductor elements or for connection between each semiconductor element and an external circuit is reduced accordingly. As a result, the wire width decreases, and the wire resistance increases. This causes the problems described below.
The wire resistance causes different voltages to be applied to the semiconductor elements although the same voltage must be applied to each semiconductor element. As a result, current concentrates on a particular portion of the semiconductor elements. The concentration of current may lower the reliability of the semiconductor elements, shorten the meltdown life of the wires, and shorten the electromigration life of the wires. Although the DMOSFET is less likely to have secondary breakdown than a bipolar transistor, the DMOSFET may be broken by such local concentration of current.